BicMO logic circuit

ABSTRACT

A logic circuit comprises an input section for inputting a signal and outputting an output signal through a CMOS inverter circuit; an output section having first darlington-connected bipolar transistors and a bipolar transistor to the first bipolar transistors in the shape of a totem pole, and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistors; and a control section having CMOS transistors operated on the basis of the ouptut signal of the input section, and controlling the operations of the first and second bipolar transistors of the output section through the CMOS transistors in accordance with the output signal of the input section.

The present invention relates to a logic circuit using bipolartransistors and CMOS transistors to reduce cost in electric power andprovide drive ability for high load and to perform their operations at ahigh speed.

BACKGROUND OF THE INVENTION

In a conventional logic circuit there are various kinds of circuitsystems including those constituted by bipolar transistors and CMOStransistors.

FIG. 1 is a diagram of a NAND gate circuit constituted by bipolartransistors. With respect to the NAND gate shown in FIG. 1, an inputstage having two input terminals A and B which include diode transistorlogic having diodes D₁ and D₂ and schottky transistors (referred to as Stransistors in the following description) Q₁ and Q₂ of NPN type, and anoutput stage which has an S transistor Q₃ and a bipolar transistor Q₄(referred to as a B transistor in the following description) of NPN typewhich are darlington-connected to each other. The output stage also hasan S transistor Q₅ connected to the transistors Q₃ and Q₄. An outputterminal OUT is connected to the connecting point between the Btransistor Q₄ and the S transistor Q₅.

When the logic gate is configured by the B transistor, a logic gatehaving drive ability for high load and operated at a high speed can beprovided by a large transfer conductance of the B transistor which isone of the characteristics thereof.

In FIG. 1, when both the input terminals A and B are in a high levelstate of voltage, the S transistor Q₁ is turned on so that an electricpath is formed from a voltage source V_(cc) through a resistor R₁, Stransistor Q₁ and a resistor R₂ to ground. Further, the S transistor Q₂is turned on so that an electric current flows along a path from thevoltage source V_(cc) through a resistor R₃, S transistor Q₂ to the baseterminal of S transistor Q₅. When either one of the input terminals Aand B is in a low level state of voltage, e.g., the input terminal A isin the low level state, an electric current flows along a path from thevoltage source V_(cc) through a resistor R₄ to a diode D₁.

Accordingly, even when the circuit is in the stationary state, theelectric current path mentioned above is formed in the circuit so thatthe power consumption is increased. When the electric current is reducedto decrease the power consumption, the circuit is not operated at a highspeed. Therefore, the circuit has been constructed by CMOS transistorsto operate the circuit at a high speed and reduce the power consumption.

FIG. 2 is a diagram of a NAND gate circuit configured by CMOStransistors. In the NAND gate circuit, an input stage having two inputterminals C and D is constructed by a P channel MOS transistor P₁(referred to as PMOS in the following description) and N channel MOStransistors (referred to as NMOS in the following description) N₁ and N₂connected in series to each other, a PMOS transistor P₂, an NMOStransistor N₃ and an NMOS transistor N₄ which are connected in series toeach other and connected in parallel to PMOS transistor P₁, NMOStransistor N₁ and NMOS transistor N₂. An output stage of the NAND gatecircuit is constructed by an inverter circuit composed of a PMOStransistor P₃ and an NMOS transistor N₅, an inverter circuit composed ofa PMOS transistor P₄ and an NMOS transistor N₆, and furthercascade-connected to the former inverter circuit. An input protectingcircuit constituted by diodes D₃, D₄ of PN junction and a resistor R₅,and diodes D₅ and D₆ of PN junction and a resistor R₆, is connected tothe respective input terminals C and D.

When the logic circuit is constructed by the CMOS transistors asmentioned above, the current drive ability is reduced and it isdifficult to operate the circuit at a high speed since the transferconductance of the MOS transistor is smaller than that of the bipolartransistor. Accordingly, the output stage of the logic circuit isconstructed by inverter circuits having the increased sizes oftransistors and being cascade-connected to each other.

However, in such a logic circuit constructed as above, an output signalis delayed by a transfer delay time t_(pd) of the inverter circuitscascade-connected to each other. Further, when the sizes of thetransistors at the output stage are increased, the circuit is increasedin size, which is disadvantageous in specifically providing a compactcircuit by integration.

Further, when the sizes of the transistors at the output stage areincreased, the ON resistances of the transistors are reduced.Accordingly, when an output signal is overshot or undershot, the ONresistances of the transistors cannot absorb the overshoot or undershootof the output signal in a resonant circuit formed by an inductancecomponent of a wiring connected to an output terminal OUT and a capacitycomponent of a load, thereby generating ringing and causing an error inoperation in the worst case.

Therefore, the input protecting circuit of the diodes of the PN junctionand resistor is connected to the input terminals C and D, and isefficient with respect to surge noise. However, it is difficult tosufficiently restrict the ringing since the voltage drop V_(F) in theforward direction of the diodes of PN junction is about 0.7 volt.

As mentioned above, when the logic gate is constructed by bipolartransistors, the load-drive ability and the speed of operation areimproved, but the power consumption is increased, and the speed ofoperation is reduced when the power consumption is reduced.

When the logic gate is constructed by only CMOS transistors, the powerconsumption can be reduced, but the load-drive ability is reduced and itis difficult to operate the circuit at a high speed. When the sizes ofthe transistors at the output stage are increased to improve theload-drive ability, the structure of the circuit is increased in sizeand it is difficult to sufficiently restrict the ringing. Therefore, insuch constructions, it is difficult to reduce power consumption, improveload-drive ability and speed in operation, and restrict ringing.

SUMMARY OF THE INVENTION

To solve the problems mentioned above, an object of the presentinvention is to provide a logic circuit for reducing power consumption,improving load-drive ability and speed in operation, and restrictingringing.

With the above object in view, the present invention resides in a logiccircuit comprising an input section for outputting a signal by reversingan input signal by a CMOS inverter, an output section having bipolartransistors darlington-connected to each other and a bipolar transistorconnected to these bipolar transistors the output section outputtinglogically operated results with respect to the input signal from theconnection point of the connected bipolar transistor, and a controlsection having CMOS transistors and a transistor for discharging a basecharge of the darlington-connected bipolar transistors and the connectedbipolar transistor when the output signal of the output section ischanged from a low level of voltage to a high level, the control sectioncontrolling the operations of the respective bipolar transistors of theoutput section in accordance with the output signal of the inputsection.

In the logic circuit of the present invention, the operations of thebipolar transistors connected to each other and constituting the outputsection are controlled by the control section having the CMOStransistors. The base charge of one of the bipolar transistors isdischarged through the transistors constituting the control section,thereby reducing a through electric current flowing through the outputsection and reducing the power consumption and performing logicoperation with respect to the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more apparent from the following preferredembodiments thereof in conjunction with the accompanying drawings inwhich:

FIG. 1 is a diagram of a conventional logic circuit constituted bybipolar transistors;

FIG. 2 is a diagram of another conventional logic circuit constituted byCMOS transistors;

FIG. 3 is a diagram showing the construction of a logic circuitaccording to a first embodiment of the present invention;

FIG. 4 is a view showing waveforms of signals in operation of the logiccircuit of FIG. 3;

FIG. 5 is a diagram showing the construction of a logic circuitaccording to a second embodiment of the present invention;

FIG. 6 is a diagram showing the construction of a logic circuitaccording to a third embodiment of the present invention; and

FIG. 7 is a diagram showing the construction of a logic circuitaccording to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will now be describedwith reference to the accompanying drawings.

FIG. 3 is a diagram showing the construction of a logic circuit inaccording with a first embodiment of the present invention. In FIG. 3,the logic circuit is consituted by a mixture of bipolar transistors andCMOS transistors, and comprises an input section I, a control section IIhaving CMOS transistors, and an output section III composed of bipolartransistors, constituting an AND gate or NOR gate having two inputterminals A and B.

In FIG. 3, the input section I has inverter circuits I₁ and I₂ composedof PMOS and NMOS transistors. The input terminal A is connected to aninput of the inverter circuit I₁ through an input protecting circuitcomposed of a schottky diode (referred to as an S diode in the followingdescription) D₁₁ and a resistor R₁₁. The input terminal B is connectedto an input of the inverter circuit I₂ through an input protectingcircuit composed of an S diode D₁₂ and a resistor R₁₂.

The control section II controls the operation of the output sectiondescribed later, and comprises a switching circuit 1 for operating thelogic gate shown in FIG. 3 as an AND gate or NOR gate, PMOS transistorsP₁₃, P₁₄ and P₁₅ connected in series to each other, NMOS transistors N₁₄and N₁₅ connected in parallel to each other, and an S transistor Q₁₄ anda resistor R₁₄.

When the logic gate is operated by the switching circuit 1 as an ANDgate, an input terminal a and an output terminal b, and an inputterminal c and an output terminal d are respectively short-circuitedtherebetween. When the logic gate is operated by the switching circuit 2as a NOR gate, inverter circuits are respectively inserted between theinput and output terminals a and b, and the input and output terminals cand d.

The gate terminals of the PMOS transistor P₁₅ and the NMOS transistorN₁₃ are connected to an output of the inverter circuit I₂ through theswitching circuit 1. The gate terminals of the PMOS transistor P₁₄ andthe NMOS transistor N₁₄ are connected to an output of the invertercircuit I₁ through the switching circuit 1. The gate terminal of thePMOS transistor P₁₃ is connected to the drain terminals of the NMOStransistors N₁₃ and N₁₄.

The S transistor Q₁₄ is disposed to discharge the base charge of the Stransistor Q₁₃ constituting the output section III described later, andis inserted between ground and the source terminals of the NMOStransistors N₁₃ and N₁₄. The base terminal of the S transistor Q₁₄ isconnected to the drain terminal of the PMOS transistor P₁₅ and isconnected to ground through a resistor R₁₄.

The output section III has an S transistor Q₁₁ and a B transistor Q₁₂darlington-connected to each other, and an S transistor Q₁₃ connected tothe transistors Q₁₁ and Q₁₂ in the shape of a totem pole. An outputterminal OUT is connected to the connection point between the Btransistor Q₁₂ and the S transistor Q₁₃. The base terminal of the Stransistor Q₁₁ is connected to a voltage source V_(cc) through aresistor R₁₃, and is connected to the drain terminals of the NMOStransistors N₁₃ and N₁₄. The base terminal of the S transistor Q₁₂ isconnected to the base terminal of the S transistor Q₁₁ through an Sdiode D₁₃. The base terminal of the S transistor Q₁₃ is connected to thesource terminals of the NMOS transistors N₁₃ and N₁₄.

The operation of the logic circuit in the first embodiment of thepresent invention mentioned above will now be described with referenceto FIG. 4 showing waveforms of signals in FIG. 3.

In the following description, the input and output terminals a and b,and the input and output terminals c and d are respectivelyshort-circuited in the switching circuit 1, and the logic gate in FIG. 3is operated as an AND gate.

When the input terminal A is in a high level state of voltage, an outputof the inverter circuit I₁ becomes a low level state of voltage, and thePMOS transistor P₁₄ is turned on, the NMOS transistor N₁₄ is turned off,and the potential of the output terminal OUT in this state is changed asfollows.

Namely, in such a state, when the input terminal B is in the low levelstate, an input of the inverter circuit I₂, i.e., the potential at pointD is in the high level state, and the NMOS transistor N₁₃ is turned on.Accordingly, the S transistor Q₁₁ and the B transistor Q₁₂ are turnedoff, the S transistor Q₁₃ is turned on and its output is in the lowlevel state.

When the input terminal B is changed from the low level to the highlevel, the potential at point D begins to be decreased from the highlevel to the low level. The PMOS transistor P₁₅ is turned on when thepotential at point D becomes less than a potential which is the sourcepotential V_(S15) of the PMOS transistor P₁₅ minus a threshold voltageV_(T15) of the PMOS transistor P₁₅. Thus, an electric current issupplied from a voltage source V_(cc) to the base terminal of the Stransistor Q₁₄ through the PMOS transistors P₁₃, P₁₄ and P₁₅ so that theS transistor Q₁₄ is turned on. Accordingly, the base charge of the Stransistor Q₁₃ is discharged to ground through the S transistor Q₁₄ sothat the S transistor Q₁₃ is rapidly turned off.

When the S transistor Q₁₄ is turned on, an electric current flows alonga path from the resistor R₁₃ through the NMOS transistor N₁₃ to the Stransistor Q₁₄. The time at which the S transistor Q₁₄ is turned on isdelayed by making the electric current, which begins to be supplied tothe base terminal of the S transistor Q₁₄, to flow through the resistorR₁₄, thereby reducing a through electric current flowing through thetransistors Q₁₂ and Q₁₃.

The NMOS transistor N₁₃ is turned on until the potential at point D isfurther reduced and has become a voltage which is a voltage V_(BE13)between the base and emitter of the S transistor Q₁₃ plus a thresholdvoltage V_(T13) of the NMOS transistor N₁₃. However, the drain currentof the NMOS transistor N₁₃ begins to be gradually reduced since thevoltage between the gate and source thereof is reduced. When thepotential at point D has reached the voltage (V_(BE13) +V_(T13)), theNMOS transistor N₁₃ is turned off. The potential at point C is increasedin accordance with a time constant between the resistor R₁₃, the drainsof the NMOS transistors N₁₃ and N₁₄, and the parasitic capacities in theS diodes D₁₃ and D₁₄.

When the potential at point C is increased, the S transistor Q₁₁ isturned on so that the B transistor Q₁₂ is turned on and the outputterminal OUT is changed from the low level state to the high levelstate. When the potential at point C is further increased and has becomegreater than voltage V_(cc) -V_(T13) which is the threshold voltage ofthe PMOS transistor P₁₃, the PMOS transistor P₁₃ is turned off. Thus,the electric current is not supplied to the base terminal of the Stransistor Q₁₄, and the charge accumulated in this base terminal isdischarged to ground through the resistor R₁₄ so that the S transistorQ₁₄ is turned off.

Accordingly, when the output terminal OUT is changed from the low levelstate to the high level state, the base charge of the S transistor Q₁₃is discharged to ground through the S transistor Q₁₄, thereby reducingthe through electric current flowing from the voltage source V_(cc)through the B transistor Q₁₂ and the S transistor Q₁₃ to ground.

In such a state, when the input terminal B is changed to the low levelstate, the potential at point D begins to be increased from the lowlevel to the high level so that the NMOS transistor N₁₃ is turned on andan electric current begins to flow through the NMOS transistor N₁₃.Thus, when the potential at point C begins to be decreased and hasbecome less than the threshold voltage V_(cc) -V_(T13) of the PMOStransistor P₁₃, the PMOS transistor P₁₃ is turned on, and all of thePMOS transistors P₁₃, P₁₄ and P₁₅ are temporarily turned on. However,the potential at point D is increased and the PMOS transistor P₁₅ isimmediately thereafter turned off so that all of the PMOS transistorsP₁₃, P₁₄ and P₁₅ are turned on for a very short time.

The electric current, which is the voltage V_(BE) between the base andemitter of the S transistor Q₁₄ divided by the resistance R of theresistor R₁₄, in the electric current flowing through the base terminalof the S transistor Q₁₄ is absorbed by the resistor R₁₄. Accordingly,the S transistor Q₁₄ is held to be turned off.

Accordingly, an electric current is supplied to the base terminal of theS transistor Q₁₃ from the voltage source V_(cc) through the resistor R₁₃and the NMOS transistor N₁₃. Further, the base charge of the Btransistor Q₁₂ is supplied through the S diode D₁₃ and the charge of theoutput terminal OUT is supplied through the S diode D₁₄. Thus, the Stransistor Q₁₃ is turned on and the S transistor Q₁₁ and the Btransistor Q₁₂ are turned off, and the output terminal OUT is changedfrom the high level state to the low level state.

The same results as above can be provided even when the input terminal Bis in the high level state and the state of the input terminal A ischanged, and can further be provided even when inverter circuits areinserted between the input and output terminals a and b, and between theinput and output terminals c and d of the switching circuit 1.

Although the bipolar transistors are used in the above logic circuit,the electric current in the active and normal states in the circuit isgreatly reduced, and the power consumption can be approximately reducedto the one in a circuit constructed by only CMOS transistors. Further,since the output stage is constructed by the bipolar transistors, thehigh load drive ability can be obtained and the speed in operation canbecome high. Further, the ON resistance of the bipolar transistors atthe output stage can restrict the ringing since the electriccurrent-voltage characteristics thereof are not linear ones and the ONresistance is greater than that of a CMOS transistor having a similardrive ability.

Further, the input protecting circuit in the logic circuit of thepresent invention is constituted by the S diode which is fast inresponse and which has a small voltage drop in the forward direction incomparison with diode of PN junction. Therefore, the ringing, whichtends to be generated when the wiring connected to the input terminal islong, can be restricted in comparison with an input protecting circuitusing the diode of the PN junction.

In the construction of the logic circuit shown in FIG. 3, both the PMOStransistors P₁₄ and P₁₅ are changed to be turned on in accordance withinput change in the following two cases.

(1) When the output terminal d of the switching circuit 1 is in the lowlevel state and the PMOS transistor P₁₄ is turned on, the outputterminal b of the switching circuit 1 is changed from the high levelstate to the low level state and the PMOS transistor P₁₅ is changed fromthe turning-off state to the turning-on state.

(2) When the output terminal b of the switching circuit 1 is in the lowlevel state and the PMOS transistor P₁₅ is turned on, the outputterminal d of the switching circuit 1 is changed from the high levelstate to the low level state and the PMOS transistor P₁₄ is changed fromthe turning-off state to the turning-on state.

In item (1), since the PMOS transistor P₁₄ is turned on, the voltageV_(DS) between the source and drain of the PMOS transistor P₁₄ is 0volt. Further, since the NMOS transistor N₁₃ is turned on and the PMOStransistor P₁₃ is turned on, the potential of the source of the PMOStransistor P₁₅ is equal to the potential of the voltage source V_(cc).Accordingly, when the potential of the gate of the PMOS transistor P₁₅is changed from the high level state to the low level state, the PMOStransistor P₁₅ is rapidly turned on, thereby rapidly performing theswitching operation from the turning-off state to the turning-on state.

In item (2), since the PMOS transistor P₁₄ is turned off, the potentialof the source of the PMOS transistor P₁₅ is equal to the thresholdpotential of the PMOS transistor P₁₅ so that the PMOS transistor P₁₅ isin the cutoff state. Accordingly, when the potential of the gate of thePMOS transistor P₁₄ is changed from the high level state to the lowlevel state, the potential of the source of the PMOS transistor P₁₅ isincreased and the voltage V_(GS) between the gate and source of the PMOStransistor P₁₅ is increased after the PMOS transistor P₁₄ has beenturned on.

Accordingly, with respect to the input change in item (2), the PMOStransistor P₁₅ is turned on after the PMOS transistor P₁₄ has beenturned on, and the switching operation from the turning-off state to theturning-on state is slightly delayed in comparison with the case of item(1), thereby generating differences with respect to the responsecharacteristics of the logic circuit at the time of the high leveloutput.

FIG. 5 shows a second embodiment of the present invention constructedsuch that the response characteristics become the same as mentionedabove. FIG. 5 is a diagram showing the construction of a logic circuitin accordance with the second embodiment of the present invention inwhich the PMOS transistors P₁₄ and P₁₅ shown in FIG. 3 are replaced by asame threshold circuit 3 enclosed by a dotted line of FIG. 5 in whichthe threshold values are the same. The other construction of FIG. 5 issimilar to the construction of the logic circuit shown in FIG. 3, andtherefore the same reference numerals in FIG. 5 are the same orcorresponding portions in FIG. 3.

In FIG. 5, the same threshold circuit 3 is constituted by four PMOStransistors P₁₆, P₁₇, P₁₈ and P₁₉.

The PMOS transistors P₁₆ and P₁₇ are connected in series to each otherbetween the drain terminal of the PMOS transistor P₁₃ and the baseterminal of the S transistor Q₁₄. The gate terminal of the PMOStransistor P₁₆ is connected to the output terminal b of the switchingcircuit 1, and the gate terminal of the PMOS transistor P₁₇ is connectedto the output terminal d of the switching circuit 1.

The PMOS transistors P₁₈ and P₁₉ are connected in parallel to the PMOStransistors P₁₆ and P₁₇, and connected in series to each other, and areconnected in series to each other between the drain terminal of the PMOStransistor P₁₃ and the base terminal of the S transistor Q₁₄. The gateterminal of the PMOS transistor P₁₈ is connected to the output terminald of the switching circuit 1, and the gate terminal of the PMOStransistor P₁₉ is connected to the output terminal b of the switchingcircuit 1.

The operation of the same threshold circuit 3 constructed as above willnow be described when the PMOS transistors P₁₆ and P₁₇, and the PMOStransistors P₁₈ and P₁₉ connected in series to each other arerespectively turned on. In this case, in the switching circuit 1, theinput and output terminals a and b, and the input and output terminals cand d are respectively short-circuited to operate the logic circuits asAND gate.

First, the input terminal A is in the high level state, and the inputterminal B is in the low level state. The operation of the logic circuitwill be described in these states when the input terminal B is changedfrom the low level state to the high level state.

When the input terminal A is in the high level state and the inputterminal B is in the low level state, the output terminal b of theswitching circuit 1 is in the high level state and the output terminal dthereof is in the low level state, and the PMOS transistors P₁₆ and P₁₉are turned off, and the PMOS transistors P₁₇ and P₁₈ are turned on.Accordingly, the potential of the source of the PMOS transistor P₁₇ isequal to the threshold voltage of the PMOS transistor P₁₇, and thepotential of the source of the PMOS transistor P₁₉ is equal to thepotential of the voltage source.

In such a state, when the input terminal B is in the high level state,the output terminal b of the switching circuit 1 is changed from thehigh level state to the low level state, and the PMOS transistors P₁₆and P₁₉ are changed from the turning-off state to the turning-on state.

At this time, since the potential of the source of the PMOS transistorP₁₉ is equal to the potential of the voltage source, the PMOStransistors P₁₈ and P₁₉ are turned on before the PMOS transistor P₁₆ ischanged from the turning-off state to the turning-on state and both thePMOS transistors P₁₆ and P₁₇ are turned on. Therefore, the electriccurrent flowing out of the voltage source V_(cc) through the PMOStransistor P₁₃ is supplied to the base terminal of the S transistor Q₁₄through the PMOS transistors P₁₈ and P₁₉ immediately after the outputterminal b of the switching circuit 1 is changed from the high levelstate to the low level state.

Next, the input terminal A is in the low level state, and the inputterminal B is in the high level state, and the operation of the logiccircuit will be described in these states when the input terminal A ischanged from the low level state to the high level state.

When the input terminal A is in the low level state and the inputterminal B is in the high level state, the output terminal b of theswitching circuit 1 is in the low level state and the output terminal dthereof is in the high level state, and the PMOS transistors P₁₆ and P₁₉are turned on, and the PMOS transistors P₁₇ and P₁₈ are turned off.Accordingly, the potential of the source of the PMOS transistor P₁₉ isequal to the threshold potential of the PMOS transistor P₁₉.

In such a state, when the input terminal A is changed from the low levelstate to the high level state, the output terminal d of the switchingcircuit 1 is changed from the high level state to the low level state,and the PMOS transistors P₁₇ and P₁₈ are changed from the turning-offstate to the turning-on state.

At this time, since the potential of the source of the PMOS transistorP₁₇ is equal to the potential of the voltage source, the PMOStransistors P₁₆ and P₁₇ are turned on before the PMOS transistor P₁₈ ischanged from the turning-off state to the turning-on state, and both thePMOS transistors P₁₈ and P₁₉ are turned on. Therefore, the electriccurrent flowing out of the voltage source V_(cc) through the PMOStransistor P₁₃ is supplied to the base terminal of the S transistor Q₁₄through the PMOS transistors P₁₆ and P₁₇ immediately after the outputterminal d of the switching circuit 1 is changed from the high levelstate to the low level state.

As mentioned above, there is the first case in which both the inputterminals A and B are changed to the high level state by changing theinput terminal A from the low level state to the high level state, andthe second case in which both the input terminals A and B are changed tothe high level state by changing the input terminal B from the low levelstate to the high level state. The PMOS transistors changing from theturning-off state to the turning-on state in the same threshold circuit3 are different from each other with respect to the first and secondcases, but the same threshold circuit 3 is symmetrically constructedwith respect to the output terminals b and d of the switching circuit 1.Accordingly, the same threshold circuit 3 is similarly operated in thefirst and second cases in that the electric current is supplied to thebase terminal of the S transistor Q₁₄ from the voltage source V_(cc).

Accordingly, the logic circuit in the second embodiment has the effectssimilar to the ones of the first embodiment, and the responsive speed ofthe same threshold circuit 3 can be the same irrespective of change ofthe input level, and the responsive characteristics of the logic circuitat the time of the high level output can be same.

The similar effects can be obtained even when inverter circuits arerespectively connected between the input and output terminals a and b,and between the input and output terminals c and c of the switchingcircuit 1, and the logic circuit is operated as a NOR gate.

FIG. 6 is a diagram showing the construction of a logic circuit inaccordance with a third embodiment of the present invention.

In FIG. 3, the drain terminal of the PMOS transistor P₁₃ and the baseterminal of the S transistor Q₁₄ are connected to each other through thePMOS transistors P₁₄ and P₁₅ connected in series to each other. Incontrast to FIG. 3, in the logic circuit of FIG. 6, the drain terminalof the PMOS transistor P₁₃ and the base terminal of the S transistor Q₁₄are connected to each other through PMOS transistors P₂₁ and P₂₂ whichare connected in parallel to each other. The gate terminal of the PMOStransistor P₂₁ is connected to the output terminal b of the switchingcircuit 1, and the gate terminal of the PMOS transistor P₂₂ is connectedto the output terminal d of the switching circuit 1. Accordingly, thelogic circuit is operated as an OR gate by the switching circuit 1 inwhich the input and output terminals a and b, and the input and outputterminals c and d are respectively short-circuited, and the logiccircuit is operated as a NAND gate by the switching circuit 1 in whichinverter circuits are respectively inserted between the input and outputterminals a and b, and between the input and output terminals c and d ofthe switching circuit 1.

Further, in FIG. 3, the base terminals of the respective S transistorsQ₁₁ and Q₁₃ are connected to each other through the NMOS transistors N₁₃and N₁₄ which are connected in parallel to each other. In contrast toFIG. 3, in the logic circuit of FIG. 6, NMOS transistors N₂₁ and N₂₂ areconnected in series to each other, and NMOS transistors N₂₃ and N₂₄connected in series to each other, and connected in parallel to eachother between the base terminals of the respective S transistors Q₁₁ andQ₁₃. The gate terminals of the NMOS transistors N₂₁ and N₂₄ areconnected to the output terminal b of switching circuit 1, and the gateterminals of the NMOS transistors N₂₂ and N₂₃ are connected to theoutput terminal d of the switching circuit 1. According to such aconstruction, the switching operation of the S transistor Q₁₃ is notchanged irrespective of the output change of the switching circuit 1.

In the construction of the logic circuit constructed above, the sameeffects as the ones in the first embodiment can be obtained even whenthe logic circuit of FIG. 6 is operated as an OR gate or a NAND gate,and the responsive characteristics of the logic circuit can be the samewith respect to the output change of the switch circuit 1.

FIG. 7 is a diagram showing the construction of a logic circuit inaccordance with a fourth embodiment of the present invention andincludes bipolar transistors Q₁ -Q₄, PMOS M₁ and M₂, NMOS M₃, andresistors R₁ -R₄. In contrast to FIG. 3, the logic circuit of FIG. 7 isoperated as a buffer circuit by constituting the input section I by oneinverter circuit I₃, and by short-circuiting input and output terminalsa and b of a switching circuit 2 therebetween, and is operated asinverter circuit by inserting an inverter circuit between the input andoutput terminals a and b. The switching operation of an output signal issimilar to the one in FIG. 3.

According to the construction of the logic circuit mentioned above, theeffects similar to the ones in the first embodiment of FIG. 3 can beobtained even in a buffer circuit or an inverter circuit.

In the logic circuits in the first to fourth embodiments of the presentinvention, the inverter circuits I₁, I₂ and I₃ receiving an input signalare constituted by CMOS transistors, and the level of the input signalis equal to the levels of the CMOS transistors. However, the inputsignal at the transistor-transistor logic level can be also used bysetting the threshold voltage of PMOS transistors constituting theinverter circuits I₁, I₂ and I₃ higher than the normal voltage such asabout 0.8 volt.

As mentioned above, according to the present invention, the operation ofbipolar transistors constituting an output section and connected to eachother is controlled by a control section having CMOS transistors, andthe base charge of one of the bipolar transistors is discharged througha transistor constituting the control section when the bipolartransistors are switched, thereby reducing a through electric currentflowing through the output section. Accordingly, in the logic circuit ofthe present invention, power consumption can be reduced, high load driveability can be obtained, and the operation can be performed at a highspeed.

Further, since the output section is constituted by using the bipolartransistors, the ringing generated in an output terminal can besufficiently restricted.

What is claimed is:
 1. A logic circuit comprising:first and secondbipolar transistors connected in series between a high voltage sourceand a low voltage source; an output terminal connected between anemitter terminal of said first transistor and a collector terminal ofsaid second transistor; a first MOS transistor of a first channel typeconnected between respective base terminals of said first and secondbipolar transistors; an element having a first terminal connected tosaid high voltage source and a second terminal connected to the baseterminal of said first bipolar transistor for increasing voltage levelat the base terminal of said first bipolar transistor when said firstMOS transistor is turned off and decreasing the voltage level at thebase terminal of said first bipolar transistor when said first MOStransistor is turned on; a third bipolar transistor connected betweenthe base terminal of said second bipolar transistor and said low voltagesource; and a second MOS transistor of a second channel type opposite tosaid first channel type and a third MOS transistor connected to saidsecond MOS transistor in series, a base terminal of said second MOStransistor being supplied with a logical input signal, said third MOStransistor having a base terminal connected to the base terminal of saidfirst or second bipolar transistors and being adapted to be turned onwhen said first MOS transistor is turned on and to be turned off whensaid first MOS transistor is turned off.
 2. The logic circuit of claim 1wherein said first bipolar transistor is part of a circuit comprising adarlington pair.
 3. The logic circuit of claim 1 further comprising aresistor connected between the base terminal of said third bipolartransistor and said low voltage source.
 4. The logical circuit of claim1, wherein said element is a resistor.
 5. The logic circuit of claim 1further comprising a fourth MOS transistor of said first channel typeconnected in parallel with said first MOS transistor, a base terminal ofsaid fourth MOS transistor being supplied with a second logical inputsignal, and a fifth MOS transistor of said second channel type connectedin series between said second and third MOS transistors, a base terminalof said fifth MOS transistor being supplied with said second logicalinput signal.
 6. The logic circuit of claim 1 further comprising afourth MOS transistor of said first channel type connected in parallelwith said first MOS transistor, a base terminal of said fourth MOStransistor being supplied with a second logical input signal, andwherein said second MOS transistor is part of a circuit comprising afifth MOS transistor connected in series with said second MOStransistor, said second and fifth MOS transistors being connected inparallel with sixth and seventh MOS transistors which are connected inseries to each other, respective bases of said fifth and sixth MOStransistors being supplied with said second logical input signal andsaid seventh MOS transistor being supplied with said logical inputsignal supplied to said second MOS transistor.
 7. The logic circuit ofclaim 1 further comprising a fourth MOS transistor of said secondchannel type connected in parallel to said second MOS transistor, a baseterminal of said fourth MOS transistor being supplied with a secondlogical input signal, and wherein said first MOS transistor is part of acircuit which includes a fifth MOS transistor connected in series tosaid first MOS transistor, said first and fifth MOS transistors beingconnected in parallel to sixth and seventh MOS transistors which areconnected in series to each other, and wherein respective base terminalsof said fifth and seventh MOS transistors being supplied with saidsecond logical input signal and respective base terminals of said firstand sixth MOS transistors being supplied with the logical input signalsupplied to said second MOS transistor.